Nano@Tech Seminar Series

Friday, October 12th at 12 noon

Marcus Nanotechnology Building Conference Room

 Topic:  High Volume Manufacturing Challenges at Intel

Dr. Ivan Murzin

Staff Process Engineer

Intel Corp.

Moore's law is the observation that over the history of computing hardware the number of transistors on integrated circuits doubles approximately every two years. For the past 45 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing Complementary Metal–Oxide–Semiconductor (CMOS) transistor performance and density. For much of this time, Moore’s Law transistor scaling meant “classic” Dennard scaling. However, in recent years, Dennard scaling has become less influential. More specifically, for generations after the 130 nm node (90 nm, 65 nm, 45 nm, 32 nm, 22 nm) performance enhancers (such as SiGe induced strain and high-k metal gate) have been added to continue to drive the transistor roadmap forward. In this talk, scaling transistor innovation will be overviewed as a part of the pursuit of power constraint, standby power dominated devices.  Scaling imposes great challenges on the processing technology involved in semiconductor manufacturing as well as drives the need to pursue advanced materials.  We will highlight the examples of such challenges in development of low-k advanced dielectrics and thin film deposition methods (atomic layer deposition) as well the ways of overcoming these.

Speaker:  Dr. Ivan Murzin is a Staff Process Engineer in F17 P840 Program in Technology and Manufacturing Division at Intel. He has 20+ years of experience in Thin Films (both PVD and CVD), ion beam surface modification and Material Analysis. Ivan has a PhD in Material Science (1992) and holds the certificate in Management from Harvard University Extension School (2007). Ivan has more than 30 papers published in the international journals and conferences and holds 5 US patents. Ivan authored 50+ white papers on process and equipment improvements while being the process engineer at Intel. In 2011, Dr. Murzin received the “Excellence of a Faculty as an Educator and Faculty Advisor Award” category for the FSM “Excellence in Technical Leadership Advancement through Education” Annual Award for College of Engineering.  In 2012 he became Adjunct Professor at Georgia Tech via the Intel College of Engineering program. In addition to thin film deposition processes, Dr. Murzin's current professional interests include magnetic, chemical, electrical and mechanical properties of material interfaces.

Pizza lunch is provided, however we ask that you limit yourself to two slices so as many attendees as possible can be accommodated.

Event Details


  • Friday, October 12, 2012
    12:00 pm - 1:00 pm
Location: Marcus Nanotechnology Building Conference Room
Phone: (404) 385-0276

For More Information Contact

David Gottfried -