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Title: Trumping the Multicore Memory Hierarchy with Hi-Spade
Speaker: Dr. Phillip B. Gibbons, Intel Labs
Abstract: The goal of the Hi-Spade project is to enable a hierarchy-savvy approach to algorithm design and systems for emerging multicore cache/memory/storage hierarchies. The project seeks to create abstractions, tools and techniques that (i) assist programmers and algorithm designers in achieving effective use of emerging hierarchies and (ii) leads to systems that better leverage the new capabilities these hierarchies provide. Our abstractions seek a sweet spot that exposes only what must be exposed for high performance, while our techniques deliver that good performance across a variety of platforms and platform-sharing scenarios. Key enablers of our approach include internally-deterministic parallel programming, new cache abstractions, novel thread schedulers, and effective use of available flash devices (and other NVM technologies such as phase change memory). Our performance evaluations consider a variety of application kernels involving sorting, graphs, geometry, graphics, string processing, and database operations. This talk surveys our key results to date, covering ~10 conference papers.
Bio: Phillip B. Gibbons is a Principal Research Scientist at Intel Labs and Principal Investigator (together with Prof. Greg Ganger) for the new Intel Science and Technology Center for Cloud Computing, a $15M research partnership with Carnegie Mellon, Georgia Tech, Princeton, and UC Berkeley. He received his Ph.D. in Computer Science from the University of California at Berkeley in 1989. He joined Intel Labs (Intel Research) in 2001 after 11 years at (AT&T and Lucent) Bell Laboratories. Gibbons is an Adjunct (Full) Professor in the Computer Science Department at Carnegie Mellon University.
Gibbons’ research areas include parallel computing, databases/big data systems, cloud computing, sensor networks, distributed systems, and computer architecture. His publications span theory and systems, across a broad range of computer science (e.g., papers in ASPLOS, CCS, CIDR, EuroSys, JFP, PACT, PLDI, PODC, PPoPP, SIGMOD, SPAA, ToN and VLDBJ since 2010), and have been cited over 11,000 times (including 31 papers cited over 100 times). Gibbons has co-authored award-winning papers at ICDE, ISCA(2), NSDI, PLDI, and SIGMOD, as well as 13 other papers that were selected for “best papers” journal issues for their respective conferences (including ICFP, PODC, PODS, SIGCOMM, SPAA, and VLDB). Gibbons has served on 60+ international program committees, including being program chair/co-chair/vice-chair/area-chair for the SPAA, SenSys, IPSN, Sigmod, ICDE, and DCOSS conferences. He is Editor-in-Chief for the just approved ACM Transactions on Parallel Computing, an Associate Editor for the Journal of the ACM (covering parallel computing and architecture), and past Associate Editor for both the IEEE Transactions on Computers and the IEEE Transactions on Parallel and Distributed Systems. He is an inventor on 17 U.S. Patents. Gibbons is a Fellow of the ACM.